The go-to highest parallelism test system for discrete MOSFETs, IGBTs, SiC, GaN to hard-docking wafer test system capability.
True Parallelism Static Test
Integration of test head based system for cost optimisation on MOSFET, IGBT, SiC, GaN devices with Dynamic RDSON.
Integration Advancement
Multi-site and multi-task capable with auxiliary equipment unification on avalanche and thermal resistance test requirements.
Open Architecture
Specific customer software test methodology proliferation using C++ programming and open hardware design enabling custom circuitry on test head board.
Key Features
Maximum Voltage and Current Ratings:
±2000V/20A (DC Static) for 16 sites in TRUE parallel
High current DC up to 160A in serial
Dynamic RDSON at 1000V/10A in TRUE parallel
100kHz-1MHz ZMU (±40V DC Bias up to ±2000V option)
Avalanche and thermal resistance integration option
Encompassing the STS8200 full floating VI resource supporting the test head advanced circuitry for high-density parallel test system for soft or hard-docking handler integration.
All AccoTEST test systems include comprehensive and no licence-based UI interface with full support for debug tools, waveform generation, and database generation tools with analytics.
